描述:
Analog Frequency Multiplier
Analog Frequency Multiplier
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生命周期:量产
概述
The Analog Frequency Multiplier (AFM) is the industry’s first ‘Balanced Oscillator’ utilizing analog multiplication of the fundamental frequency (at quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase-locked loop (PLL), in CMOS technology.This world’s best performing AFM products can achieve up to 800MHz output frequency with little jitter or phase noise deterioration. In ddition, the low frequency input crystal requirement makes the AFM the most affordable high-performance timing-source in the market.PL565-68 product utilizes low-power CMOS technology and is housed in Green / RoHS compliant 16-pin TSSOP, and 16-pin 3x3 QFN packages.
特性
- Non-PLL frequency multiplication by 2
- Input frequency from 62.5-160MHz
- PL565-68: 125-320MHz
- Low phase noise and jitter (equivalent to fundamental crystal at the output frequency)
- RMS phase jitter <100fs (12kHz-20MHz)
- RMS random period jitter <2ps
- -142 dBc/Hz @100kHz offset from the carrier
- -155 dBc/Hz @10MHz offset from the carrier
- High linearity pull range (typ. 5%)
- VCXO, set pullability ±100ppm ~ ±200ppm
- Low input frequency eliminates the need for expensive crystals
- Differential output levels: LVPECL
- Single 3.3V, ±10% power supply
- Optional industrial temperature range (-40°C to +85°C)
- Available in 16-pin Green/RoHS compliant 3x3 QFN packages and as die
概述
The Analog Frequency Multiplier (AFM) is the industry’s first ‘Balanced Oscillator’ utilizing analog multiplication of the fundamental frequency (at quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase-locked loop (PLL), in CMOS technology.This world’s best performing AFM products can achieve up to 800MHz output frequency with little jitter or phase noise deterioration. In ddition, the low frequency input crystal requirement makes the AFM the most affordable high-performance timing-source in the market.PL565-68 product utilizes low-power CMOS technology and is housed in Green / RoHS compliant 16-pin TSSOP, and 16-pin 3x3 QFN packages.
特性
- Non-PLL frequency multiplication by 2
- Input frequency from 62.5-160MHz
- PL565-68: 125-320MHz
- Low phase noise and jitter (equivalent to fundamental crystal at the output frequency)
- RMS phase jitter <100fs (12kHz-20MHz)
- RMS random period jitter <2ps
- -142 dBc/Hz @100kHz offset from the carrier
- -155 dBc/Hz @10MHz offset from the carrier
- High linearity pull range (typ. 5%)
- VCXO, set pullability ±100ppm ~ ±200ppm
- Low input frequency eliminates the need for expensive crystals
- Differential output levels: LVPECL
- Single 3.3V, ±10% power supply
- Optional industrial temperature range (-40°C to +85°C)
- Available in 16-pin Green/RoHS compliant 3x3 QFN packages and as die
PL565-68 系列参数
属性 | 参数值 |
---|---|
Package | QFN-16L(3x3) |
SubGroup2 | VCXO |
Supply Voltage | 3.3 |
# of Outputs | 1 |
OutputLogic | LVPECL |