The N32901U1DN is built on the ARM926EJ-S CPU core and integrated with JPEG codec, CMOS sensor interface, 32-channel SPU ( Sound Processing Unit ) , ADC , DAC, for meeting various kinds of application needs while saving the BOM cost.  The combination of ARM926 @ 200 MHz , synchronous DRAM, 2D BitBLT accelerator, CMOS image sensor interface, LCD panel interface, USB 1.1 Host & USB2.0 HS Device makes the N32901U1DN the best choice for LCD ELA devices.Maximum resolution for the N32901U1DN is QVGA ( 320x240 ) @ TFT LCD panel. The 2D BitBLT accelerator accelerates the graphic compution to make the rendering smooth and off-load CPU to save power consumption.The N32901U1DN is well-positioned in terms of cost/performance for the applications which bitmap graphics is extensively used or CMOS Image Sensor ( CIS ) interface is required.To meet the different requirement of the overall system BOM cost, the different size of DRAM is stacked with N3290x main SoC into one package, that is, multi-chip package ( MCP ) .  The N32901U1DN is particularly designed with the 128-pin LQFP package and the 1Mbitx16 SDRAM is stacked inside the MCP.  Total BOM cost could be reduced by employing 2-layer PCB along with the elimination of damping resistors, EMI prevention components, etc. Advantages including, but not limited to, less PCB space, shorter lead time, and higher / reliable production yield.