module ad57x4_mdl (
// user system clock
input wire i_sys_clk, // clock ipcore 100m
input wire i_sys_rst, // clock ipcore reset
// user config data
input wire [ 23 : 0 ] i_reg_config,
input wire [ 23 : 0 ] i_vout_range,
input wire [ 23 : 0 ] i_init_vout,
// user decode dac data
input wire [ 15 : 0 ] i_cnl0_data,
input wire [ 15 : 0 ] i_cnl1_data,
input wire [ 15 : 0 ] i_cnl2_data,
input wire [ 15 : 0 ] i_cnl3_data,
// user decode uart data done
input wire i_user_done,
// dac hardware ports
output wire o_dac_sync,
output wire o_dac_sclk,
output wire o_dac_sdin,
output wire o_dac_clr,
output wire o_dac_ldac
);
wire o_send_done;
ad57x4_step_blk u_ad57x4_step_blk (
.i_sys_clk ( i_sys_clk ),
.i_sys_rst ( i_sys_rst ),
.i_reg_config ( i_reg_config ),
.i_vout_range ( i_vout_range ),
.i_init_vout ( i_init_vout ),
.i_cnl0_data ( i_cnl0_data ),
.i_cnl1_data ( i_cnl1_data ),
.i_cnl2_data ( i_cnl2_data ),
.i_cnl3_data ( i_cnl3_data ),
.i_user_done ( i_user_done ),
.o_send_done ( o_send_done ),
.o_dac_sync ( o_dac_sync ),
.o_dac_sclk ( o_dac_sclk ),
.o_dac_sdin ( o_dac_sdin )
);
ad57x4_ldac_blk u_ad57x4_ldac_blk (
.i_sys_clk ( i_sys_clk ),
.i_sys_rst ( i_sys_rst ),
.i_send_done ( o_send_done ),
.o_dac_ldac ( o_dac_ldac )
);
assign o_dac_clr = ( i_sys_rst == 1'b0 );
endmodule
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