顶层文件 ad5360_mdl.v
module ad5360_mdl
(
i_sys_clk ,
i_sys_rst ,
AD5360_SYNC_n ,
AD5360_SCLK ,
AD5360_SDI ,
AD5360_SDO ,
AD5360_CLR_n , //Asynchronous Clear Input (Level Sensitive, Active Low).
AD5360_RESET_n , //Digital Reset Input
AD5360_BUSY_n , //Digital Input/Open-Drain Output. BUSY is open drain when it is an output.
AD5360_LDAC_n ,//Load DAC Logic Input (Active Low).
i_cnl0_mdata,
i_cnl1_mdata,
i_cnl2_mdata,
i_cnl0_cdata,
i_cnl1_cdata ,
i_cnl2_cdata ,
i_cnl0_regdata ,
i_cnl1_regdata ,
i_cnl2_regdata ,
i_cnl3_regdata ,
i_cnl4_regdata ,
i_cnl5_regdata ,
i_cnl6_regdata ,
i_cnl7_regdata ,
i_cnl8_regdata ,
i_cnl9_regdata ,
i_cnl10_regdata ,
i_cnl11_regdata ,
i_cnl12_regdata ,
i_cnl13_regdata ,
i_cnl14_regdata ,
i_cnl15_regdata ,
i_user_m_done ,
i_user_c_done ,
i_user_d_done ,
i_cnl0_rf_mdata ,
i_cnl1_rf_mdata ,
i_cnl2_rf_mdata ,
i_cnl0_rf_cdata ,
i_cnl1_rf_cdata ,
i_cnl2_rf_cdata ,
i_user_rf_done
);
input i_sys_clk;
input i_sys_rst;
output AD5360_SYNC_n;
output AD5360_SCLK;
output AD5360_SDI;
input AD5360_SDO;
output AD5360_CLR_n;//当CLR为低电平时,每个DAC输出缓冲级(VOUT0至VOUT15)的输入被切换到相关SIGGNDx引脚上的外部设置电位。当CLR为低时,忽略所有LDAC脉冲。
output AD5360_RESET_n;
inout AD5360_BUSY_n;
output AD5360_LDAC_n;
input wire [ 15 : 0 ] i_cnl0_mdata;
input wire [ 15 : 0 ] i_cnl1_mdata;
input wire [ 15 : 0 ] i_cnl2_mdata;
// input wire [ 15 : 0 ] i_cnl3_mdata;
input wire [ 15 : 0 ] i_cnl0_cdata;
input wire [ 15 : 0 ] i_cnl1_cdata;
input wire [ 15 : 0 ] i_cnl2_cdata;
// input wire [ 15 : 0 ] i_cnl3_cdata;
input wire [ 15 : 0 ] i_cnl0_regdata;
input wire [ 15 : 0 ] i_cnl1_regdata;
input wire [ 15 : 0 ] i_cnl2_regdata;
input wire [ 15 : 0 ] i_cnl3_regdata;
input wire [ 15 : 0 ] i_cnl4_regdata;
input wire [ 15 : 0 ] i_cnl5_regdata;
input wire [ 15 : 0 ] i_cnl6_regdata;
input wire [ 15 : 0 ] i_cnl7_regdata;
input wire [ 15 : 0 ] i_cnl8_regdata;
input wire [ 15 : 0 ] i_cnl9_regdata;
input wire [ 15 : 0 ] i_cnl10_regdata;
input wire [ 15 : 0 ] i_cnl11_regdata;
input wire [ 15 : 0 ] i_cnl12_regdata;
input wire [ 15 : 0 ] i_cnl13_regdata;
input wire [ 15 : 0 ] i_cnl14_regdata;
input wire [ 15 : 0 ] i_cnl15_regdata;
input wire i_user_m_done;
input wire i_user_c_done;
input wire i_user_d_done;
input wire [ 15 : 0 ] i_cnl0_rf_mdata;
input wire [ 15 : 0 ] i_cnl1_rf_mdata;
input wire [ 15 : 0 ] i_cnl2_rf_mdata;
input wire [ 15 : 0 ] i_cnl0_rf_cdata;
input wire [ 15 : 0 ] i_cnl1_rf_cdata;
input wire [ 15 : 0 ] i_cnl2_rf_cdata;
input wire i_user_rf_done;
wire o_send_done;
ad5360_mdl_ldac M_ldac_ad5360(
.i_sys_clk (i_sys_clk), // clock ipcore 100m
.i_sys_rst (i_sys_rst), // clock ipcore reset
.i_send_done (o_send_done),
.o_dac_ldac (AD5360_LDAC_n )
);
ad5360_mdl_step M_step_ad5360(
.i_sys_clk (i_sys_clk),
.i_sys_rst (i_sys_rst),
.AD5360_SYNC_n (AD5360_SYNC_n),
.AD5360_SCLK (AD5360_SCLK),
.AD5360_SDI (AD5360_SDI),
.AD5360_SDO (AD5360_SDO),
.AD5360_CLR_n (AD5360_CLR_n) , //Asynchronous Clear Input (Level Sensitive, Active Low).
.AD5360_RESET_n (AD5360_RESET_n), //Digital Reset Input
.AD5360_BUSY_n (AD5360_BUSY_n), //Digital Input/Open-Drain Output. BUSY is open drain when it is an output.
.i_cnl0_mdata (i_cnl0_mdata),
.i_cnl1_mdata (i_cnl1_mdata),
.i_cnl2_mdata (i_cnl2_mdata),
.i_cnl0_cdata (i_cnl0_cdata),
.i_cnl1_cdata (i_cnl1_cdata),
.i_cnl2_cdata (i_cnl2_cdata),
.i_cnl0_regdata (i_cnl0_regdata),
.i_cnl1_regdata (i_cnl1_regdata),
.i_cnl2_regdata (i_cnl2_regdata),
.i_cnl3_regdata (i_cnl3_regdata),
.i_cnl4_regdata (i_cnl4_regdata ),
.i_cnl5_regdata (i_cnl5_regdata ),
.i_cnl6_regdata (i_cnl6_regdata ),
.i_cnl7_regdata (i_cnl7_regdata ),
.i_cnl8_regdata (i_cnl8_regdata ),
.i_cnl9_regdata (i_cnl9_regdata ),
.i_cnl10_regdata (i_cnl10_regdata ),
.i_cnl11_regdata (i_cnl11_regdata ),
.i_cnl12_regdata (i_cnl12_regdata ),
.i_cnl13_regdata (i_cnl13_regdata ),
.i_cnl14_regdata (i_cnl14_regdata ),
.i_cnl15_regdata (i_cnl15_regdata ),
.i_user_m_done (i_user_m_done),
.i_user_c_done (i_user_c_done),
.i_user_d_done (i_user_d_done),
.o_send_done (o_send_done ),
.i_user_rf_done (i_user_rf_done),
.i_cnl0_rf_mdata (i_cnl0_rf_mdata),
.i_cnl1_rf_mdata (i_cnl1_rf_mdata),
.i_cnl2_rf_mdata (i_cnl2_rf_mdata),
.i_cnl0_rf_cdata (i_cnl0_rf_cdata),
.i_cnl1_rf_cdata (i_cnl1_rf_cdata),
.i_cnl2_rf_cdata (i_cnl2_rf_cdata)
);
endmodule
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